This design in not intended to be easily reproducible.
Some parts are prohibitively expensive to purchase new.
Comments and suggestions are welcome.
Schematics and the PCB layout will be available for download under the GPL.
This spectrum and network analyzer uses digital signal processing to eliminate
many components in the IF section. The sampling rate is 125 MHz.
It consists of transmit and recieve sections which are similar in construction.
Recieve section
The input signal is shifted up to a 2.15 GHz 1st IF by mixing with a local oscillator (LO) which ranges from 2.15 to 4 GHz.
The 1st IF is passed through an interdigital bandpass filter with a bandwidth of 8 MHz.
The 1st IF is then mixed with a fixed LO to create a 2nd IF centered on 30 MHz. This signal is digitized by an ADC sampling at 125 MHz.
A digital down converter in the FPGA will reduce the sample rate to 500 kHz so that the signal can be handled by a DSP.
Transmit section
The FPGA drives a DAC which creates an IF centered on 32 MHz. This IF is mixed with the fixed LO
to generate a 2.15 GHz IF. An interdigital band pass filter identical to the one in the recieve section is
used to eliminate the image. The 2.15 GHz IF is then mixed with the variable LO to shift it to the desired output frequency.
Master clock
The master clock is a 10 MHz ovenized crystal oscillator.
This oscillator frequency can be adjusted by a DAC.
A Saronix S1569 125 MHz VCXO with LVPECL outputs is used to clock the ADCs and DACs. It is phase locked to the 10 MHz master clock.
1st LO PLL (PLL1)
The 1st LO uses a YIG oscillator. This is a magnetically tuned oscillator.
More information can be found here (Warning: 6.3 MB PDF).
These cost around $1000 if purchased new, but they can be found on the surplus market for much less.
I paid $30 for the one used in the analyzer.
It has 2 tuning coils: a main tuning coil with a sensitivity of 20 MHz/ma and a FM coil with a lower sensitivity.
The main tuning coil current is set by a DAC to get the YIG to approximately the correct frequency.
The FM coil is controlled by an ADF4106 PLL IC. The reference is the 10 MHz master clock. The channel spacing is 2.5 MHz.
2nd LO PLL (PLL2)
The 2nd LO also uses the ADF4106 PLL IC, but uses a UMC UMZ-169-A16 VCO module.
It is always locked to 2120 MHz.
Parts
TI DAC904E 14 bit DAC
Linear Technology LTC2208 16 bit 130 MHz ADC
Linear Technology LT1993-10 ADC driver amp
Xilinx XC3SD1800A FPGA
PLX NET2272 USB 2.0 device interface
Analog Devices ADF4106 PLL
Hittite Microwave HMC-213 mixer (Front end)
Hittite Microwave HMC-316 mixer (IF)
Minicircuits GALI-6F MMIC amp (Output driver)
Avago MGA-82563 MMIC amp (LO drivers, IF amps)
Hittite Microwave HMC-545 RF switch
Downloads - Warning: these are incomplete works in progress
All licensed under the GPL
Schematics: gEDA gschem
PCB Layout PCB
Last updated 3/1/2008
Suggestions or comments are welcome. m-a-i-l at this domain name. Sorry, for having to list the address this way, but the old one got 300 spams per day. website@dlharmon.com